1. Field of the Invention
The invention relates to a clock and data recovery circuit, more particularly to a clock and data recovery circuit and a method of adjusting loop bandwidth of the same.
2. Description of the Related Art
FIG. 1 illustrates a conventional clock and data recovery circuit that includes: a voltage controlled oscillator 11 for generating an output clock according a control voltage signal; a loop filter 17 connected electrically to the voltage controlled oscillator 11 for outputting the control voltage signal according to a current output that is composed of first and second current outputs; a first charge pump 14 connected electrically to the loop filter 17 for outputting the first current output according to a frequency error signal; a second charge pump 16 connected electrically to the loop filter 17 for outputting the second current output according to a phase error signal; a frequency divider 12 connected electrically to the voltage controlled oscillator 11 for frequency dividing the output clock; a frequency detector 13 connected electrically to the first charge pump 14 and the frequency divider 12 for comparing the output clock frequency-divided by the frequency divider 12 with a reference signal and for outputting the frequency error signal according to a frequency difference therebetween; a phase detector 15 connected electrically to the voltage controlled oscillator 11 and the second charge pump 16 for comparing the output clock from the voltage controlled oscillator 11 with input data and for outputting the phase error signal according to a phase difference therebetween; and a sampling circuit 18 connected electrically to the voltage controlled oscillator 11 for sampling the input data based on the output clock from the voltage controlled oscillator 11 and for outputting output data.
To ensure stability of the conventional clock and data recovery circuit, it is desirable that loop bandwidth (FPLL,−3dB) of a phase-locked loop part thereof be not greater than 1/10 of the frequency (Fin) of the input data, which can be expressed as follows:
      F          PLL      ,                        -          3                ⁢                                  ⁢        dB              ≈                    I                  P          ⁢                                          ⁢          2                    ·              R        LF            ·              K        VCO                    2      ⁢      π        ≤            1      10        ⁢          F      in      where IP2 is the value of the second current output from the second charge pump 16, RLF is the impedance of the loop filter 17, and KVCO is the gain of the voltage controlled oscillator 11.
The frequency of the input data may change. As such, if the loop bandwidth (FPLL,−3dB) is set to 1/10 of the highest frequency (Fin) of the input data, jitter of the output clock becomes large when the frequency of the input data becomes low. On the other hand, if the loop bandwidth (FPLL,−3dB) is set to 1/10 of the lowest frequency (Fin) of the input data, the tracking speed of the phase-locked loop part becomes slow when the frequency (Fin) of the input data becomes high, thereby resulting in longer settling time of the conventional clock and data recovery circuit.
In view of the above configuration, since the loop bandwidth (FPLL,−3dB) is fixed, there is a trade-off between short settling time for conventional clock and data recovery circuit and small jitter for the output clock.